1. Field of the Invention
The present invention relates to a semiconductor device, in particular to a semiconductor device including transistors forming a differential pair. More particularly, the present invention relates to an arrangement of diodes for providing protection against the change in characteristics of the transistors forming the differential pair.
2. Description of the Background Art
In a differential amplifier, a mixer and others, a differential transistor pair operating in a differential manner is arranged at an input stage for processing a differential input. It is generally known that even a minute difference in characteristics in such a differential transistor pair would cause various problems such as an offset voltage. In particular, when there is a difference in threshold voltage and/or drain current of transistors employed in the differential pair at the input section, a significant problem frequently occurs with regard to circuit characteristics.
To avoid the occurrence of difference in transistor characteristics, attentions are often paid in creating a layout, such as to align the centroid positions of transistor elements. However, some issues remain unresolved only through the measure on the transistor layout. One of such issues is the problem of characteristics degradation called antenna effect, which is discussed in Japanese Patent Laying-Open No. 2002-141421, for example. In manufacture of the semiconductor device that includes an MOS transistor (Insulated Gate Field Effect Transistor) as a component, charge stress is applied to an interconnection layer during a plasma process. The charge stress negatively affects the characteristics of the MOS transistor, which is referred to the antenna effect.
Specifically, in the manufacturing process of semiconductor devices, especially in an interconnection step, plasma etching is often used to pattern an interconnection layout into a desired geometry. In the plasma etching step, plasma charged particles are accumulated on a patterned metal line and the metal line turns into a charged-up state. When the metal line is connected to a gate of an MOS transistor via a contact hole, charged-up plasma charged particles flow into and are accumulated on a gate electrode layer which is formed, for example, of polysilicon. Because of the electric charges accumulated on the gate electrode layer, the electric potential of the gate surface rises to create a large electrical potential difference across a gate insulation film located under the gate electrode layer, whereby a large voltage stress is applied onto the gate insulation film.
Because of the voltage stress, the gate insulation film would be broken down. Even if such break down would not occur, because of the electric field created by the electric potential difference across the gate insulation film, electrons would be sometimes trapped in the gate insulation film, whereby the characteristics of the MOS transistor after the manufacturing, such as the threshold voltage Vth and drain current Ids would change. Such phenomenon is called antenna effect. The degree of influence by such effect depends on the ratio (antenna ratio) of an area of the interconnection layer on which plasma charged particles generated during the plasma etching are accumulated to an area of the gate insulation film.
The antenna effect can occur at any transistors. However, the degree of the change of characteristics of the transistor varies according to the feature of the metal interconnection section connected to the transistor and is not same for all transistors. At the input stage of the differential circuit, a combination of transistors with identical characteristics, in other words, matched characteristics, is required for achieving an accurate differential operation. When a phenomenon due to the antenna effect occurs at the input stage of such differential circuit, the characteristics of the differential circuit is significantly degraded. To prevent such characteristics degradation, the following two solutions are proposed in the above-referenced patent publication:
(1) to make the length and other features of the metal lines connected to the transistors of differential circuit input stage the same; and
(2) to connect a diode for discharging electric charges at the gate of each transistor in the input stage of the differential circuit.
The above-referenced patent publication discloses provision of dummy interconnection lines in the arrangement for discharging the accumulated electric charges to a substrate region through the diode, to make identical the lengths of interconnection lines of input signals to the differential stage transistors. However, such arrangement requires the region for placing the dummy interconnection lines to increase the interconnection area. In addition, depending on the layout, such dummy interconnection could not placed in some cases. If the dummy interconnection lines should be laid out, the circuit layout may be negatively limited, whereby the efficient arrangement of transistors and interconnection line could not be achieved.
As described in the above-referenced patent publication, it is possible to suppress the degradation of transistor characteristics through the discharge of the electric charges accumulated during plasma etching to the substrate region by connecting the diodes to the gates of differential pair transistors. However, as the substrate region is utilized as one electrode of the diode, the noise generated in the substrate region is transmitted to a differential stage input signal line via the diode, to be superimposed onto an input signal, thereby impeding the accurate differential amplification of the input signals.
It could not be predicted where the noise of interest is generated in a semiconductor circuit device. Noise is generated in a region outside the circuit including the differential stage and transmitted to the substrate region. As the generation source of such noise, various circuits/ interconnection lines can be considered, including a digital circuit, a high frequency circuit and a power source line. Although the noise is partially attenuated during its propagation through the substrate, it is significantly amplified when it is input to differential pair transistors, which amplify a minute potential difference, via a capacitance component of the diode. If the magnitude of noise applied to the differential inputs of the differential pair transistors are equal with each other, the noise can be cancelled out through the function of common mode component rejection of the differential stage.
However, the distances from the noise source to the diodes are not always the same. If the distances from the noise source to the diodes arranged at the input of differential pair transistors are not the same, the magnitudes of noise will change accordingly. Therefore, the function of common mode rejection characteristic of the differential stage is not sufficient for the noise rejection and the residual noise will be amplified.
In the above-referenced patent publication, consideration is given only to the removal of plasma charged particles generated during the plasma etching process and no consideration is given to the influence of noise transmitted to the diodes via the substrate region.
An object of the present invention is to provide a semiconductor device capable of performing an accurate differential operation without being influenced by a substrate noise while matching the characteristics of a differential transistor pair.
Another object of the present invention is to provide a semiconductor device having a differential input stage with n excellent immunity against the antenna effect and the substrate noise.
A semiconductor device according to the present invention includes: a first transistor; a second transistor arranged electrically parallel with the first transistor; a first group of diodes including a plurality of diode elements connected electrically in parallel to a first terminal of the first transistor; and a second group of diodes including a plurality of diode elements connected in parallel electrically to a first terminal of the second transistor. A position of center of gravity made by diode elements in the first group of diodes overlaps with a position of center of gravity made by the diode elements in the second group of diodes.
As the diode elements are arranged such that the centers of gravity of diode elements included in the first and second groups of diodes overlap with each other, the first and second groups of diodes are subject to identical effect from the noise from any direction, and transmit the noise component of the same magnitude to the first terminals of the first and second transistors accordingly. Thus, the total amount of noise will be equal and noise rejection will be securely performed through the common mode rejection characteristics of the differential stage and the accurate differential operation will be achieved.
In addition, with the arrangement of the first and second groups of diodes, the change in transistor characteristics accompanying antenna effect on the first terminals of the first and second transistors can be prevented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.